1. Field of the Invention
The present invention relates to voltage generating circuits of semiconductor devices, and more particularly to a back-bias voltage generating circuit for preventing electron injection into the substrate that is appropriate for a semiconductor device having CMOS transistors.
2. Description of the Prior Art
As illustrated in FIG. 1, a conventional back-bias generating circuit receives oscillating signals in the form of an alternate current waveform through inverter X4. The back-bias generating circuit also includes first pumping portion 100 having node N2, to which input driving signals are applied, and second pumping portion 200 having node N12, to which input driving signals are applied through inverter X5.
First pumping portion 100 includes PMOS transistor M1 coupled at its source to power source VCC and NMOS transistor M2, the gates of which are connected to node N2 and the drains of which are connected in common with each other and also connected to the gate of NMOS transistor M5, the source of which is grounded to ground terminal VSS. The drain of NMOS transistor M5 is connected through node N5 to the source of NMOS transistor M2. Inverters X1, X2 and X3 and pumping capacitor M4 are connected in series between nodes N2 and N5, forming nodes N6 to N8. NMOS transistor M3 has its drain connected to node N5. The gate and source of NMOS transistor M3 are connected together and to back-bias terminal VBB.
Second pumping portion 200 includes PMOS transistor M6, three NMOS transistors M7, M8 and M10, three inverters X6, X7 and X8, and pumping capacitor M9. Except for receiving input signals through inverter X5, these circuit elements are arranged in the same manner as with the circuit elements of first pumping portion 100.
Therefore, oscillation signal OSC is passed through inverter X4 to invert a high potential signal into a low potential signal, and vice versa. A low potential signal at node N2 is applied to the gates of PMOS transistor M1 and NMOS transistor M2, and PMOS transistor M1 is turned on, and NMOS transistor M2 is turned off. During the saturation condition of PMOS transistor M1, power source VCC causes NMOS transistor M5 to turn on.
At the same time, the low potential signal is inverted through three inverters X1, X2 and X3 into a high potential signal, and thus VCC is applied to one end of pumping capacitor M4. The other electrode of pumping capacitor M4 is connected to node N5, and thus VSS is applied to the other electrode.
Thereafter, oscillation signal OSC is reversed and passed through inverter X4 to invert the low potential signal into a high potential signal. The high potential signal at node N2 is applied to the gates of PMOS transistor M1 and NMOS transistor M2, and PMOS transistor M1 is turned off, and NMOS transistor M2 is turned on. Thus, NMOS transistor M5 turns off.
At the same time, the high potential signal of node N2 is inverted through three inverters X1, X2 and X3 into a low potential signal, and thus VSS is applied to one end of pumping capacitor M4. The other electrode of pumping capacitor M4 is connected to node N5 which is now in a floating state or connected to terminal VBB through transistor M3.
Pumping capacitor M4 has a coupling effect with the other electrode of the pumping capacitor, which becomes a negative voltage lower (more negative) than VSS.
Therefore, when the voltage difference between node N5 and back-bias terminal VBB approaches a threshold voltage, switching NMOS transistor M3 is turned on, and the voltage on back-bias terminal VBB may be lowered by the charge of the pumping capacitor.
Similarly, second pumping portion 200 is operated identically to first pumping portion 100, but the input driving signal is applied through inverter X5 to node N12, and the pumping signal opposite to that of pumping capacitor M4 is generated at pumping capacitor M9. First and second pumping portions 100 and 200 are pumped in turn in opposite phase to each other.
The conventional back-bias generating circuit causes the voltage values of common nodes N5 and N14 to be lowered in to a high degree over the back-bias voltage VBB. FIG. 4 is a waveform illustrating the voltages of VBB and node N5. During the time when the voltage of node N5 becomes lower than the voltage on terminal VBB, an increase in the number of electrons injected from the nodes of the pumping capacitors into the substrate may be caused, which thereby may result in abnormal operation of a cell such as latch-up.
Also, the applying of the back-bias voltage to a switching transistor requires substantial time for dropping the back-bias voltage by a desirous voltage because the conductance value of the switching transistor is small.
Accordingly, it is an object of the present invention to provide a back-bias voltage generating circuit of a semiconductor device for keeping a stable back-bias voltage at a predetermined level.
Another object of the present invention is to provide an inner voltage generating circuit of a semiconductor device for preventing electron injection into a substrate appropriate for a semiconductor device.
Another object of the present invention is to provide a back-bias voltage generating circuit of a semiconductor device for compensating the pumping voltage with respect to the back-bias voltage.
Still another object of the present invention is to provide a back-bias voltage generating circuit of a semiconductor device for enhancing the conduction property of a switching portion .with respect to the back-bias voltage.